As the size of transistors shrinks with every new generation of semiconductor devices, there has been a significant decrease in the gate-oxide thickness of transistors. Unlike thick gate gate-oxide transistors, thin gate-oxide transistors may easily be damaged even when there are relatively small voltage spikes. This is especially prominent when there is a transient discharge of static charges into or out of the transistors, arising as a result of human handling or machine contact.
Generally, an electrostatic discharge (ESD) protection circuit may be utilized to resolve such transient discharge of static charges. The ESD protection circuit may allow the excessive charges to flow through a pathway that is isolated from electrical pathways that are connected to functional circuitry on the semiconductor device.
ESD protection schemes may be implemented at a system level or a device level, depending on the particular circuit design. Specific implementations may be targeted to resolve specific types of ESD occurrences. As an example, a system level ESD protection scheme protects the overall system from ESD occurrences while a device level ESD protection scheme may protect a specific circuit within a device from ESD occurrences.
Generally, the ESD protection circuit at the device level may include a dual-diode architecture. However, with the shrinking dimensions of transistors, the conventional dual-diode architecture may not be able to handle an ESD event, especially the one modelled after a charge-device modelling (CDM) technique. Although, designers may have resolved the problems of dual-diode architecture with shrinking transistors by increasing the size of the ESD protection circuit, it has been at a great expense of circuit speed.